FPGA Parallel output timing to satisfy input timing

Let's say a FPGA reads flip-flop D and outputs Q on the second rising edge of a CLK (figeure1). How can this satisfy the input setup time [TpdSU] of another device (figure2)?Do they generally not use the same CLK for the flip-flops and the output CLK towards another device?Or does a input device read the data on the 3th rising edge of the CLK?

Maybe I'm completely off and it is something different.